Hard
EST. TIME: 45 minFlip-Flops and Shift Registers
Design and verification of basic Flip-Flops (SR, JK, D, T) and Shift Registers.
Theory
Flip-Flops are 1-bit memory elements.
- SR FF: Basic Set-Reset. Invalid state when S=R=1.
- JK FF (7476): Eliminates invalid state. Toggles when J=K=1.
- D FF (7474): Data latch. Output follows input on clock edge.
Shift Registers (74194/74164): Used for data storage and movement (SISO, SIPO, PISO, PIPO).
Procedure
- Select a Flip-Flop type. Connect inputs and Clock.
- Verify state transitions on clock pulses.
- Connect multiple FFs to form a Shift Register. Shift data through the chain step-by-step.